Integrated circuit with borderless contacts
US6228777A · kind A · utility
14Cited by
25References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 8, 1999 |
| Grant date | May 8, 2001 |
| Priority date | — |
| Expiry date | Jun 8, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76834
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit comprising a conductive region formed on a semiconductor substrate, a silicate glass layer formed on the conductive region, and an etch stop layer formed on the silicate glass layer. The integrated circuit also includes a borderless contact that is coupled to the conductive region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.