Inventor · Portland, OR, US

Scott Thompson

15Patents

9h-index

18Co-inventors

65Inventor score

Filing activity: Jul 3, 1995 → Oct 17, 2007

Most-cited inventions

Patent	Title	Area	Cited by	Status
US6624032B2	Structure and process flow for fabrication of dual gate floating body integrated MOS transistors	Electricity	51	Expired
US6020244A	Channel dopant implantation with automatic compensation for variations in critical dimension	Electricity	47	Expired
US6392271B1	Structure and process flow for fabrication of dual gate floating body integrated MOS transistors	Electricity	43	Expired
US5976939A	Low damage doping technique for self-aligned source and drain regions	Electricity	38	Expired
US6228777A	Integrated circuit with borderless contacts	Electricity	14	Expired
US5877072A	Process for forming doped regions from solid phase diffusion source	Electricity	14	Expired
US6800887B1	Nitrogen controlled growth of dislocation loop in stress enhanced transistor	Electricity	12	Expired
US7226824B2	Nitrogen controlled growth of dislocation loop in stress enhanced transistor	Electricity	9	Expired
US7312485B2	CMOS fabrication process utilizing special transistor orientation	Electricity	9	Expired
US6294823A	Integrated circuit with insulating spacers separating borderless contacts from the well	Electricity	8	Expired
US7187057B2	Nitrogen controlled growth of dislocation loop in stress enhanced transistor	Electricity	7	Expired
US5874344A	Two step source/drain anneal to prevent dopant evaporation	Electricity	6	Expired
US6515351B2	Integrated circuit with borderless contacts	Electricity	4	Expired
US7888710B2	CMOS fabrication process utilizing special transistor orientation	Electricity	2	Active
US7723720B2	Methods and articles incorporating local stress for performance improvement of strained semiconductor devices	Electricity	2	Expired

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.