Semiconductor device
US6229363A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 4, 1999 |
| Grant date | May 8, 2001 |
| Priority date | — |
| Expiry date | Jan 4, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/087
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device having the function of generating an internal clock signal delayed by a predetermined phase by adjusting the phase of an external clock signal, includes a first clock phase circuit for roughly adjusting the phase of the external clock signal; and a second clock phase adjusting circuit for controlling the phase of the internal clock signal with higher accuracy than the first clock phase adjusting circuit. The semiconductor device having such a construction executes phase comparisons by the first and second clock phase adjusting circuits independently of each other, and when a phase control operation by the second clock phase adjusting circuit is made subordinate to that of the first clock phase adjusting circuit, the delay time of each of a plurality of delay elements inside the first clock phase adjusting circuit is set to a value larger than a power source jitter resulting from a noise of a power source and a jitter of the external clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.