Method and apparatus for accessing misaligned data from memory in an efficient manner
US6230238A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 2, 1999 |
| Grant date | May 8, 2001 |
| Priority date | — |
| Expiry date | Mar 2, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for performing mis-aligned read and write operations to a stack involves providing a memory array (110). The memory array is split into a high byte memory array (116) and a low byte memory array (112). Each memory array (112 and 116) has its own bus interface unit (114 and 118) respectively. The high byte bus interface unit (118) increments the address bits to the high byte memory array (116) on every access to compensate for mis-aligned data. However, the low byte bus interface unit (114) does not increment the address value before accessing the memory array (112). By doing so, memory is read from the memory arrays (112 and 116) in either 8 bit sizes or 16 bit sizes regardless of whether the stack structure implemented in memory array (112 and/or 116) contains aligned data or mis-aligned data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.