System and method for handling load and/or store operators in a superscalar microprocessor
US6230254A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 12, 1999 |
| Grant date | May 8, 2001 |
| Priority date | — |
| Expiry date | Nov 12, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load/store unit is provided whose main purpose is to make load requests out-of-order whenever possible to get the load data back for use by an instruction execution unit as quickly as possible. A load operation can only be performed out-of-order if there are no address collisions and no write pendings. An address collision occurs when a read is requested at a memory location where an older instruction will be writing. Write pending refers to the case where an older instruction requests a store operation, but the store address has not yet been calculated. The data cache unit returns 8 bytes of unaligned data. The load/store unit aligns this data properly before it is returned to the instruction execution unit. Thus, the three main tasks of the load/store unit are: (1) handling out of order cache requests; (2) detecting address collisions; and (3) alignment of data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.