Power electronic module packaging
US6232151A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 1, 1999 |
| Grant date | May 15, 2001 |
| Priority date | — |
| Expiry date | Nov 1, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of power electronic packaging includes a practicable and reliable method of fabricating power circuit modules and associated connections that are compatible with the standard top layer metalization of commercially available power devices. A planar single- or multi-layer membrane structure is attached to a carrier frame, and a via pattern is formed in the membrane. Power devices are aligned and attached to the planar membrane structure; a top layer interconnect structure is formed by metalizing the vias and the film; and a circuit is formed by patterning a deposited metal layer. The carrier frame is removed, and upper and lower thermal base plate sub-assemblies are attached to the power device-on-membrane structure. The planar device-on-membrane structure accommodates different types of power devices having variations in thickness. The thermal base plate sub-assemblies may include integral, high-performance heat exchangers for providing a low thermal resistance path to the ambient.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.