Method of manufacturing floating gate of stacked-gate nonvolatile memory unit
US6232184A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 10, 1999 |
| Grant date | May 15, 2001 |
| Priority date | — |
| Expiry date | Sep 10, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
Abstract
A method of manufacturing the floating gate of a stacked-gate type of nonvolatile memory unit. A gate oxide layer and a polysilicon layer are sequentially formed over a substrate. The polysilicon layer is etched to form a floating gate above the gate oxide layer. During the polysilicon etching operation, a polymeric material is also deposited on the sidewalls of the floating gate and over the exposed gate oxide. An isotropic chemical dry etching of the floating gate is carried out so that its bottom section is slightly wider than its top section. Finally, a thermal oxidation operation is carried out to form an oxide layer over the floating gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.