Method of making a floating gate memory cell
US6232185A · kind A · utility
48Cited by
3References
12Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 15, 2000 |
| Grant date | May 15, 2001 |
| Priority date | — |
| Expiry date | May 15, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
Abstract
A method for making a non-volatile memory cell having a select gate, a floating gate and a control gate of the completely self-aligned type, partially self-aligned type and non-aligned type is disclosed. Further, each of the three types of cells has a floating gate, whose linear dimension can be increased beyond the smallest lithographic feature of the process design rule
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.