Substrate board for semiconductor package
US6232551A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 18, 1999 |
| Grant date | May 15, 2001 |
| Priority date | — |
| Expiry date | Aug 18, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A substrate board structure formed by stacking a plurality of circuit layers and insulation layers on top of each other. Each circuit layer has a plurality of circuit lines and every circuit layer is separated from its neighbors by an insulation layer. The insulation layers further have a plurality of vias for connecting electrically with an electroplating bar layer. The interior surface of each via is electroplated with a metal film and the remaining space within the via is filled with a filler material. The substrate board further includes a central slot. The circuit layer on the surface of the substrate board has a plurality of first contact points and second contact points connected by circuit lines. The first contact points are close to the slot. Circuit lines that connect to the first contact points extend forward to reach the vias along the edge of the slot. Since the vias are formed on the boundary of the slot region, a portion of the metallic film within the vias is exposed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.