Multi-port semiconductor memory and compiler having capacitance compensation
US6233197A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2000 |
| Grant date | May 15, 2001 |
| Priority date | — |
| Expiry date | Mar 14, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-port semiconductor memory includes first and second data ports and a plurality of memory cells arranged in rows and columns. Each column comprises first and second pairs of complementary bit lines, which are coupled to each of the memory cells in that column. The first pair of bit lines cross one another between every N and N+1 of the memory cells the column, where N=2.sup.M and M is an integer variable greater than zero. A data inversion circuit is coupled between the first pair of bit lines and the first data port, which selectively inverts the first pair of bit lines as a function of the first port's (M+1)th row address input bit only, as measured from the least significant row address input bit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.