Fast multiplication of floating point values and integer powers of two
US6233595A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 8, 1998 |
| Grant date | May 15, 2001 |
| Priority date | — |
| Expiry date | May 8, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30014
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for performing fast multiplication in a microprocessor is disclosed. The method comprises detecting multiplication operations that have a floating point operand and an integer operand, wherein the integer operand is an integer power of two. Once detected, a multiplication operation meeting these criteria may be executed by using an integer adder to sum the integer power and the floating point operand's exponent to from a product exponent. The bias of the integer operand's exponent may also be subtracted. A product mantissa is simply copied from the floating point operand's mantissa. The floating point operand's sign bit may be inverted to form the product's sign bit if the integer operand is negative. Advantageously, the product is generated using integer addition which is faster than floating point multiplication. The method may be implemented in hardware or software.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.