Optimizing peripheral component interconnect transactions in a mixed 32/64-bit environment by eliminating unnecessary data transfers
US6233632A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 7, 1999 |
| Grant date | May 15, 2001 |
| Priority date | — |
| Expiry date | Jan 7, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for eliminating unnecessary data transfers (e.g., null data phase transfers) in a computer system. The computer system comprises a bus, a target device coupled to the bus, and an initiator device coupled to the bus. The initiator device is adapted to transfer a data byte and a signal corresponding to the data byte over the bus to the target device, wherein the signal is equal to a first value to indicate that the target device is to accept the data byte and the signal is equal to a second value to indicate that the target device is to disregard the data byte. The initiator device is further adapted to decode the signal for each of a plurality of data bytes. The initiator device withholds transferring a subset of the data bytes to the target device when the signal corresponding to each of the data bytes in the subset is equal to the second value, thereby eliminating unnecessary data transfers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.