Concurrent page tables
US6233668A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 27, 1999 |
| Grant date | May 15, 2001 |
| Priority date | — |
| Expiry date | Oct 27, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1009
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Each processor in a multi-processor system includes a process page-table-base register and a system page-table-base register. Each register identifies a different page frame containing a different instance of a top-level subtable in a multi-level page table, and both instances' contents map their respective, different page frames to the same virtual page. A first of the instances, to which the process page-table-base register refers, is used to translate virtual addresses in a process-private range, while the second instance is used for shared-range translation. When a context switch occurs, the content of the process page-table-base register is changed in accordance with the process to whose operation the processor is turning, but that of the system page-table-base register remains unchanged. Parts of the shared space are replicated in different local memory modules, and processors in different locales have different contents in their system page-table-base registers to identify different top-level-subtable instances, which map some shared-space virtual pages to different physical page frames.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.