Memory address generator capable of row-major and column-major sweeps
US6233669A · kind A · utility
2Cited by
5References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 30, 1998 |
| Grant date | May 15, 2001 |
| Priority date | — |
| Expiry date | Oct 30, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved method and structure for generating addresses of a memory array facilitates the testing of a memory cell by generating the address of any adjacent memory cell to the memory cell under test. The address generation provides for movement to any adjacent memory cell, in any direction, including north, south, east, west, northeast, northwest, southeast, and southwest. The address of any memory cell, even the address of a non-adjacent memory cell, may be selectively generated by exercising a programmable initialization feature.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.