Inventor · Fort Collins, CO, US

Jay Fleischman

30Patents
6h-index
47Co-inventors
69Inventor score

Filing activity: Oct 19, 1998 → Dec 21, 2023

Most-cited inventions

PatentTitleAreaCited byStatus
US6374370B1 Method and system for flexible control of BIST registers based upon on-chip events Physics 109 Expired
US6550023B1 On-the-fly memory testing and automatic generation of bitmaps Physics 52 Expired
US6321320A Flexible and programmable BIST engine for on-chip memory array testing and characterization Physics 35 Expired
US6249465A Redundancy programming using addressable scan paths to reduce the number of required fuses Physics 22 Expired
US6141779A Method for automatically programming a redundancy map for a redundant circuit Physics 19 Expired
US6298429A Memory address generator capable of row-major and column-major sweeps Physics 11 Expired
US11868777B2 Processor-guided execution of offloaded instructions using fixed function operations Emerging Cross-Sectional Technologies 6 Active
US8868633B2 Method and circuitry for square root determination Physics 3 Active
US6233669A Memory address generator capable of row-major and column-major sweeps Physics 2 Expired
US6175518A Remote register hierarchy accessible using a serial data line Physics 2 Expired
US9575763B2 Accelerated reversal of speculative state changes and resource recovery Physics 1 Active
US8769247B2 Processor with increased efficiency via early instruction completion Physics 1 Active
US12153926B2 Processor-guided execution of offloaded instructions using fixed function operations Emerging Cross-Sectional Technologies 1 Active
US11163688B2 System probe aware last level cache insertion bypassing Physics 1 Active
US11847062B2 Re-fetching data for L3 cache data evictions into a last-level cache Emerging Cross-Sectional Technologies 0 Active
US9268575B2 Flush operations in a processor Physics 0 Active
US10223162B2 Mechanism for resource utilization metering in a computer system Physics 0 Active
US12299445B2 Register based SIMD lookup table operations Physics 0 Active
US12204454B2 System probe aware last level cache insertion bypassing Physics 0 Active
US11550728B2 System and method for page table caching memory Physics 0 Active
US9959122B2 Single cycle instruction pipeline scheduling Physics 0 Active
US9910638B1 Computer-based square root and division operations Physics 0 Active
US8671288B2 Processor with power control via instruction issuance Emerging Cross-Sectional Technologies 0 Active
US12333309B2 Differential pipeline delays in a coprocessor Physics 0 Active
US12282428B2 Selective speculative prefetch requests for a last-level cache Physics 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.