Staggering execution of an instruction by dividing a full-width macro instruction into at least two partial-width micro instructions
US6233671A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 1998 |
| Grant date | May 15, 2001 |
| Priority date | — |
| Expiry date | Mar 31, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3828
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro instruction specifies at least two logical registers and wherein the two logical registers respectively store a first and second packed data operands having corresponding data elements. An operation specified by the single macro instruction is then performed independently on a first and second plurality of the corresponding data elements from said first and second packed data operands at different times using the same circuit to independently generate a first and second plurality of resulting data elements. The first and second plurality of resulting data elements are stored in a single logical register as a third packed data operand.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.