Method of making a memory cell having two layered tantalum oxide films
US6235572A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 17, 1999 |
| Grant date | May 22, 2001 |
| Priority date | — |
| Expiry date | Jun 17, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/716
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a DRAM having a memory cell constructed by an information storage capacitor C which is comprised of a lower electrode 54 made of a ruthenium film and an upper electrode 62 made of a capacity insulating film 61 and a titanium nitride film and which is connected in series with a memory cell selection MISFET Qs formed on the main surface of a semiconductor substrate 1. The capacity insulating film 61 is made of a multi layered film comprising two layered crystallized tantalum oxide films 56 and 58 each having a film thickness of 10 nm or less. The film thickness of the capacity insulating film 61 is set to 10 to 40 nm.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.