High performance DRAM and method of manufacture

US6235574A · kind A · utility

Assignee

• INFINEON NORTH AMERICA CORP · US

Inventors

• Dirk Tobben · Fishkill, US
• Johann Alsmeier · San Jose, US

Key dates

• Filing date: May 10, 2000
• Grant date: May 22, 2001
• Expiry date: May 10, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/09

Abstract

A process for forming a DRAM in a silicon chip that includes N-MOSFETs of the memory cells in its central area and C-MOSFETs of the support circuitry in the peripheral area. By the inclusion of a masking oxide layer over the peripheral area during the formation of the memory cells, there are formed N-MOSFETs that use N-doped polycide gates and P-MOSFETs that use P-doped polycide gates. The sources and drains include self-aligned silicide contacts.