Fabrication of differential gate oxide thicknesses on a single integrated circuit chip
US6235590A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 18, 1998 |
| Grant date | May 22, 2001 |
| Priority date | — |
| Expiry date | Dec 18, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0144
Abstract
Techniques for fabricating integrated circuits having devices with gate oxides having different thicknesses and a high nitrogen content include forming the gate oxides at pressures at least as high as 2.0 atmospheres in an ambient of a nitrogen-containing gas. In one implementation, a substrate includes a first region for forming a first device having a gate oxide of a first thickness and a second region for forming a second device having a gate oxide of a second different thickness. A first oxynitride layer is formed on the first and second regions in an ambient comprising a nitrogen-containing gas at a pressure in a range of about 10 to about 15 atmospheres. A portion of the first oxynitride layer is removed to expose a surface of the substrate on the second region. Subsequently, a second oxynitride is formed over the first and second regions in an ambient comprising a nitrogen-containing gas at a pressure in a range of about 10 to about 15 atmospheres to form the first and second gate oxides. Respective gate electrodes are formed over the first and second gate oxides. The oxynitride gates can have a nitrogen content in a range of about 0.2 to about 2.0 percent which can prevent …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.