Semiconductor memory device having high-concentration region around electric-field moderating layer in substrate
US6236085A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 10, 1997 |
| Grant date | May 22, 2001 |
| Priority date | — |
| Expiry date | Nov 10, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/90
Abstract
A semiconductor memory device comprising a source and a drain formed in a P-type semiconductor substrate and a floating gate and a control gate constituting a two-layer gate. Electric-field moderating layer is provided in the P-type semiconductor substrate to contact with a side face of the drain. P-type region is formed in contact with channel region side surface and bottom surface of the electric-field moderating layer. P-type region lower part of the P-type region in contact with the bottom surface of the electric-field moderating layer is given a lower impurity concentration than P-type region side part formed at the channel region side of the electric-field moderating layer. By this means it is possible to increase the writing speed of the semiconductor memory device while suppressing delay in the switching speed during reading operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.