Encapsulate resin LOC package and method of fabrication
US6236107A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 7, 1995 |
| Grant date | May 22, 2001 |
| Priority date | — |
| Expiry date | Jun 7, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/20753
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for fabricating small form factor semiconductor chips having high temperature resistance, good humidity and chemical resistance and good dielectric properties. The semiconductor chip includes a lead frame (10) attached to an integrated circuit die (30) by a lead-on-chip (LOC) method. Wire bonds (40) are employed to connect the integrated circuit die (30) to conduction leads (75) on the lead frame (10). After the wire bonding process, the surface of the wire bonded integrated circuit is encapsulated with a layer of resin (50) using either a direct dispensing method or by a screen printing method. The encapsulated integrated circuit may then be cured and functionally tested.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.