Multi-chip chip scale package
US6236109A · kind A · utility
68Cited by
8References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 1, 1999 |
| Grant date | May 22, 2001 |
| Priority date | — |
| Expiry date | Feb 1, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19041
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multi-chip chip scale package. A film carrier is in use. Two chips with different sizes can be disposed on the same film carrier. The flip chip technique is used to arrange each chip on each side of the film carrier face to face. A bump is formed on each chip to electrically connect with the film carrier. An insulation material is infilled between the chips to leave one side of each chip exposed. The conductive wires of the film carrier are connected with the chip directly without going through other carrier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.