Method and apparatus for detecting misalignments in interconnect structures
US6236222A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 19, 1997 |
| Grant date | May 22, 2001 |
| Priority date | — |
| Expiry date | Nov 19, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/307
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Disclosed is a method for inspecting electrical interconnections in a multi-level semiconductor device. The method includes forming an interconnect structure in the multi-level semiconductor device. The interconnect structure has a lower metallization layer that lies in a lower level and an upper metallization layer that lies in an upper level. The method includes performing a passive voltage contrast operation using a scanning electron microscope to produce an image of the upper metallization layer of the interconnect structure. The method further includes inspecting the image produced by the scanning electron microscope to determine whether a misalignment is present in the interconnect structure. Additionally, the scanning electron microscope applies a beam of electrons over a selected portion of the interconnect structure, and secondary electrons are emitted off of the upper metallization layer in response to the beam of electrons. Therefore, by examining the intensity levels of the secondary electrons, it is possible to determine whether misalignments have occurred.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.