High performance CMOS word-line driver
US6236617A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 10, 1999 |
| Grant date | May 22, 2001 |
| Priority date | — |
| Expiry date | Dec 10, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A negative wordline DRAM array having n groups of m wordlines, in which one group is driven by a group decoder circuit (having a voltage swing between ground and a circuit high voltage (2 v)) and one driver circuit in each group is exposed to a boosted wordline high voltage (2.8 v) greater than the circuit high voltage, in which the wordline driver circuits have an output stage comprising a standard nfet in series with a high threshold voltage pfet, so that, during activation, the unselected driver circuits exposed to the boosted wordline high voltage have a very low leakage through the pfet, while the selected driver circuit has a high but tolerable leakage (2 .mu.A) because Vqs on the nfet is nearly at the nfet threshold. The net active power from the entire array is less than that of a conventional configuration due to the reduced voltage swing, while the number of transistors exposed to high voltage stress is reduced from 9 to 1 and the number of buffer nfets required to reduce voltage drop across an active nfet is reduced from 8 to 1.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.