Cache memory with reduced latency
US6237064A · kind A · utility
33Cited by
5References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 23, 1998 |
| Grant date | May 22, 2001 |
| Priority date | — |
| Expiry date | Feb 23, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0897
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a method and a data processing system for accessing a memory of a data processing system, the data processing system including a first and at least a second level memory for storing information. The method includes issuing a memory request to the first level memory, and issuing the memory request to the second level memory at substantially the same time the memory request is issued to the first level memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.