Method and a related circuit for adjusting the duration of a synchronization signal ATD for timing the access to a non-volatile memory
US6237104A · kind A · utility
1Cited by
2References
18Claims
0Family size
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Key dates
| Filing date | Dec 29, 1998 |
| Grant date | May 22, 2001 |
| Priority date | — |
| Expiry date | Dec 29, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/32
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and related circuit for adjusting the duration of a pulse synchronization signal for the reading phase of memory cells in electronic memory devices which are integrated on semiconductors are discussed. The pulse synchronization signal is produced by a pulse generator when it detects a logical state commutation on at least one input terminal of a plurality of addressing input terminals of the memory cells. The method produces a logical sum between the signal produced by the generator and a pulse signal having a predetermined duration. The logical sum is used to start up the reading phase.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.