Method of quality control in semiconductor device fabrication
US6238939A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 1999 |
| Grant date | May 29, 2001 |
| Priority date | — |
| Expiry date | Apr 30, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2223/54453
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of quality control in the fabrication of semiconductor devices. During and after the deposition and patterning of two successive layers on a semiconductor wafer, two independent measures of the alignment of the two layers are obtained. From each of these measures of the alignment, there is obtained a measure of the quality of a corresponding model of the alignment. These two measures of the quality of the models are compared. In one preferred independent measure of model quality, the model is a model of upper layer misalignment that is constructed by the stepper that positions the wafer for the patterning of the upper layer. In another preferred independent measure of model quality, the model is a model of mutual layer misalignment that is determined from mutual displacement of the overlay keys of the two layers. The measures of model quality are based on the residuals of these models.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.