Low-pin-count chip package and manufacturing method thereof
US6238952A · kind A · utility
174Cited by
2References
8Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 29, 2000 |
| Grant date | May 29, 2001 |
| Priority date | — |
| Expiry date | Feb 29, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K3/202
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A low-pin-count chip package including a die pad for receiving a semiconductor chip and a plurality of connection pads electrically coupled to the semiconductor chip wherein the die pad and the connection pads have a concave profile. A package body is formed over the semiconductor chip, the die pad and the connection pads in a manner that a potion of the die pad and a portion of each connection pad extend outward from the bottom of the package body. The present invention further provides a novel method of producing the low-pin-count chip package described above.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.