Method for fabricating a nonvolatile memory including implanting the source region, forming the first spacers, implanting the drain regions, forming the second spacers, and forming a source line on the source and second spacers
US6238977A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 29, 1999 |
| Grant date | May 29, 2001 |
| Priority date | — |
| Expiry date | Mar 29, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
Abstract
A method for fabricating in a non-volatile memory is provided. The method includes providing a substrate having a memory region. A stacked gate structure is formed on the substrate at the memory region. A source region is formed abutting the stacked gate structure, and an isolation structure is formed to isolate the source region, in which a drain region is also formed abutting the stacked gate structure on the opposite side but not actually related to the invention. A first spacer is formed on each sidewall of the stacked gate structure. A conductive layer is form over the substrate and is patterned to remove a portion of a conductive layer. A remaining portion of the conductive layer covers the isolation structure and the source region so as to form a source line, which has an electrical coupling to each source region belong to a same word line. The stacked gate structure is therefore exposed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.