Process for forming MOS-gated devices having self-aligned trenches

US6238981A · kind A · utility

Assignee

• Intersil Corporation · US

Inventor

• Thomas E. Grebs · Smethport, US

Key dates

• Filing date: May 10, 1999
• Grant date: May 29, 2001
• Expiry date: May 10, 2019

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/256

Abstract

In a process for forming an MOS-gated device having self-aligned trenches, a screen oxide layer and then a nitride layer are formed on an upper layer of a semiconductor substrate. The nitride layer is patterned and etched to define a well region in the upper layer, and ions of a first conductivity type are diffused into the masked upper layer to form the well region. Ions of a second, opposite conductivity type are implanted into the well region to form a source region extending to a selected depth that defines a source-well junction. After removal of the well mask to expose the previously masked portion of the nitride layer, an oxide insulating layer providing a hard mask is formed overlying the well and source regions. The remaining previously masked portions of the nitride layer and underlying screen oxide layer are removed to expose the portion of the substrate not masked by the oxide insulating layer. The portion of the substrate thus exposed is etched to form a gate trench extending through the substrate to a selected depth beneath the well region. Insulated sidewalls and floor are formed in the gate trench, which is filled with a semiconductor material that is then planarize…