Interconnect structure using a combination of hard dielectric and polymer as interlayer dielectrics
US6239019A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 13, 1999 |
| Grant date | May 29, 2001 |
| Priority date | — |
| Expiry date | Apr 13, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A structure and method of fabrication of a semiconductor integrated circuit is described. A first patterned electrically conductive layer contains a low dielectric constant first insulating material such as organic polymer within the trenches of the pattern. A second insulating material such as a silicon dioxide or other insulating material having a greater. mechanical strength and thermal conductivity and a higher dielectric constant than the first insulating material is formed over the first patterned electrically conductive layer Vias within the second insulating material filled with electrically conductive plugs and a second patterned electrically conductive layer may be formed on the second insulating material. The structure can be repeated as many times as needed to form a completed integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.