Nitride etch stop for poisoned unlanded vias
US6239026A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 1998 |
| Grant date | May 29, 2001 |
| Priority date | — |
| Expiry date | Sep 28, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention relates to the reduction of poisoned vias in a submicron process technology semiconductor wafer by reducing the occurrence of over-etched vias through the inclusion of an etch-stop layer. Vias are created to connect conductive portions of a semiconductor wafer and if the vias are over-etched, the connection may be poor. In order to prevent the over-etching of vias, a three-step etch process is completed on a semiconductor wafer having an insulating layer, an etch-stop layer, a low dielectric constant layer, a conductive layer and a foundation layer. A via is first non-selectively etched such that the etch terminates within the insulating layer. The via is subsequently selectively etched such that the etch terminates at the etch-stop layer. Lastly, the via is again non-selectively etched through the etch-stop layer and the low dielectric constant layer such that the etch terminates at the conductive layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.