Clock multiplier using nonoverlapping clock pulses for waveform generation
US6239627A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 28, 1997 |
| Grant date | May 29, 2001 |
| Priority date | — |
| Expiry date | Aug 28, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/089
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An improved clock generator performs clock multiplication using selectable generation of clock edges. A clock multiplier divides an input clock period into N edges by generating N non-overlapping clock pulses synchronized to the period of the reference clock--these edges are selectably combined to produce an output clock with the desired multiplication and duty cycle. The sequence of non-overlapping pulses is synchronized to the period of the input reference clock, i.e., to the first harmonic of the reference clock. A pulse generator network includes N pulse generators PG1-PGN, with the output of each pulse generator being coupled to the input of the next pulse generator. When triggered, each pulse generator generates a pulse P with a leading edge and a trailing edge, and a pulse width determined by a selectable pulse-width delay signal. The pulse generator PG1 is triggered by a leading edge of the reference clock, and the remaining pulse generators PG2-PGN are triggered by the trailing edge of the pulse P from the previous pulse generator. A synchronization circuit detects phase deviations between the trailing edge of the pulse PN from pulse generator PGN and the leading edge of t…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.