Method for reading 2-bit ETOX cells using gate induced drain leakage current
US6240015A · kind A · utility
5Cited by
4References
5Claims
0Family size
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Key dates
| Filing date | Apr 7, 2000 |
| Grant date | May 29, 2001 |
| Priority date | — |
| Expiry date | Apr 7, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/565
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of reading a 2-bit memory cell having a drain, a source, a control gate, and a floating gate is disclosed. First, a voltage is applied to the source and drain to generate a gate induced drain leakage (GIDL) current. Next, a measurement is taken of a drain GIDL current at said drain and a source GIDL current at said source to determine the data stored in said memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.