Simplified peripheral logic for memory device
US6240028A · kind A · utility
7Cited by
4References
41Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 8, 2000 |
| Grant date | May 29, 2001 |
| Priority date | — |
| Expiry date | Jun 8, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1078
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A simplified address decoding and data application circuitry is provided for a double data rate memory device in which a plurality of delay elements normally used during a write operation to synchronize the timing of address data, with respect to a clock signal, are replaced by a single delay element which applies a delayed clock signal to operate shift register stages of the memory device during a write operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.