Integrated cache buffers
US6240487A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 18, 1998 |
| Grant date | May 29, 2001 |
| Priority date | — |
| Expiry date | Feb 18, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1045
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache has an array for holding data or instruction values, a buffer connected to the array, and means for accessing the buffer to retrieve a value for a processing unit. The accessing means uses wires having a pitch which is substantially equal to a wire pitch of the cache array. Multiplexers can be used with a plurality of such buffers to create a common output path. The cache can be interleaved, with the array being a first subarray, and the buffer being a first buffer, and further comprising a second subarray and a second buffer, wherein the first and second buffers separate the first and second subarrays. The invention can be applied to a store-back buffer as well as a reload buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.