Process and system for switching between an update and invalidate mode for each cache block
US6240491A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 12, 1997 |
| Grant date | May 29, 2001 |
| Priority date | — |
| Expiry date | Nov 12, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0815
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A Process for coherent management of exchanges between memories in an information system having at least two levels of memories. The information system in one embodiment is constituted by a central subsystem which can communicate with one or more peripheral subsystems by means of input-output units. The central subsystem includes several processors linked to a central memory and to the input-output units. Each processor includes an associated cache memory linked with the central memory. In operation, each processor executes the instructions of programs contained in an associated cache memory. If the cache memory does not contain the data necessary to the associated processor, the data is read in the central memory and a copy is made using memory blocks of predetermined size. The coherent management of exchange between memories is achieved by dynamically applying a management mode selected as a function of the use that is made of each block. The management mode, either update or invalidate mode, is switched based upon a predetermined threshold of ineffectiveness for a particular mode being reached. Furthermore, soft misses can be a criteria for the ineffectiveness of the invalidatio…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.