Method of fabricating a shallow doped region for a shallow junction transistor

US6242295A · kind A · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Mark S. Rodder · Dallas, US
• Douglas T. Grider · McKinney, US
• Katherine E. Violette · Dallas, US

Key dates

• Filing date: Jan 5, 1999
• Grant date: Jun 5, 2001
• Expiry date: Jan 5, 2019

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0184

Abstract

A method of forming a plurality of shallow junction transistors, the method comprising the steps of providing a substrate (10) having a first region (13) and a second region (15). The first region (13) and the second region (15) include a first channel region (14) and a second channel region (16), respectively. A first gate (22) is formed proximate the first channel region (14) and is separated from the substrate (10) by a portion of a primary insulation layer (20). A second gate (24) is formed proximate the second channel region (16) and is separated from the substrate by a portion of the primary insulation layer (20). A dopant layer (34) is then formed outwardly of the substrate (10) proximate the first region (13) and the second region (15). The dopant layer (34) proximate the first region (13) is implanted with a first dopant (40). The dopant layer (34) proximate the second region (15) is implanted with a second dopant (48). A portion of the first dopant (40) in the dopant layer (34) is diffused into the substrate (10) proximate the first region (13) to form a first shallow doped region (50), and a portion of the second dopant (48) in the dopant layer (34) is diffused into the …