Mixed mode process for embedded dram devices

US6242300A · kind A · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventor

• Chen-Jong Wang · Baoshan, TW

Key dates

• Filing date: Oct 29, 1999
• Grant date: Jun 5, 2001
• Expiry date: Oct 29, 2019

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/05

Abstract

A method for forming an embedded DRAM device with a mixed mode capacitor in the logic. The process begins by providing a semiconductor structure having a logic area and a memory area. The logic area and the memory area are separated by an isolation structure, and the logic area has a second isolation structure thereon. A first dielectric layer is formed over the semiconductor structure, and a first polysilicon layer is formed on the first dielectric layer. The first polysilicon layer and the gate dielectric layer are patterned to form an opening over the memory area. In a key step, an implant mask is formed over the first polysilicon layer with an opening over the second isolation structure, and impurity ions are implanted into the first polysilicon layer through the opening in the implant mask. After the implant mask is removed, a second dielectric layer is formed over the semiconductor structure and the first polysilicon layer. A second polysilicon layer is formed on the second dielectric layer; a silicide layer is formed on the second polysilicon layer; and a hard mask layer is formed on the silicide layer. The second polysilicon layer, the silicide layer, and the hard mask laye…