Multi-step spacer formation of semiconductor devices
US6242334A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 23, 1999 |
| Grant date | Jun 5, 2001 |
| Priority date | — |
| Expiry date | Mar 23, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/671
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a semiconductor with overetched spacer is disclosed. The method includes firstly providing a semiconductor substrate with a gate oxide layer formed thereon, and forming a polysilicon layer on the gate oxide layer. Next, a photoresist layer is formed on the polysilicon layer to define a gate area, followed by anisotropically etching the polysilicon layer and the gate oxide layer. A first dielectric layer is conformably formed, and a second dielectric layer is then formed thereon. After anisotropically etching the second dielectric layer to form a first sidewall spacer on the sidewall of the first dielectric layer, a third dielectric layer is further formed over the exposed first dielectric layer and the first sidewall spacer. Finally, the third dielectric layer and the first sidewall spacer are anisotropically etched so that a second sidewall spacer is formed on the sidewall of the first sidewall spacer, wherein top surface of the first and the second sidewall spacer is below top surface of the first dielectric layer around the gate area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.