Stacked bottom lead package in semiconductor devices
US6242798A · kind A · utility
16Cited by
13References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 29, 2000 |
| Grant date | Jun 5, 2001 |
| Priority date | — |
| Expiry date | Feb 29, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stacked bottom lead package for use in semiconductor devices includes leads that are bent along with the circumference of the body which has been premolded, wherein a chip is included inside the premolded body. The package configuration prevents solder fatigue of the lead due to heat carried via the extended lead and emitted out of the chip and decreases the area required for stacking semiconductor packages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.