Distributed decode system and method for improving static random access memory (SRAM) density
US6243287A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 27, 2000 |
| Grant date | Jun 5, 2001 |
| Priority date | — |
| Expiry date | Jan 27, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A static random access memory (SRAM) cell is provided that optimizes the density of memory cells in an array with the maximum speed possible in addressing the memory cells for reading and writing operations. The SRAM cell is divided into groups of SRAM arrays of cells with a centrally located distributed global decoder to address any individual memory cell in the SRAM array. The global decoder includes a first logic block that accepts addressing input and outputs a signal for selecting an individual column of memory cells in the SRAM array. The global decoder includes a second logic block that accepts addressing input and outputs a signal selecting an individual row of memory cells contained in the SRAM array. The global decoder may include a third logic block to decode addressing bits to produce a group select signal. Thus, the global decoder is able to select any signal memory cell in the SRAM cell for reading or writing specific logical states.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.