Inventor · Fort Collins, CO, US

John Wuu

49Patents
7h-index
57Co-inventors
72Inventor score

Filing activity: May 26, 1998 → Oct 4, 2023

Most-cited inventions

PatentTitleAreaCited byStatus
US10644826B2 Flexibile interfaces using through-silicon via technology Electricity 22 Active
US7430145B2 System and method for avoiding attempts to access a defective portion of memory Physics 22 Expired
US6366526B2 Static random access memory (SRAM) array central global decoder system and method Physics 12 Expired
US6192001A Integrated weak write test mode (WWWTM) Physics 12 Expired
US6243287A Distributed decode system and method for improving static random access memory (SRAM) density Physics 11 Expired
US6282143A Multi-port static random access memory design for column interleaved arrays Physics 10 Expired
US8276039B2 Error detection device and methods thereof Electricity 9 Active
US9575891B2 Sidecar SRAM for high granularity in floor plan aspect ratio Physics 6 Active
US9053257B2 Voltage-aware signal path synchronization Physics 5 Active
US9355743B2 Memory array test logic Physics 5 Active
US10043572B1 VSS bitcell sleep scheme involving modified bitcell for terminating sleep regions Physics 4 Active
US10431517B2 Arrangement and thermal management of 3D stacked dies Electricity 4 Active
US10509752B2 Configuration of multi-die modules with through-silicon vias Emerging Cross-Sectional Technologies 3 Active
US11804479B2 Scheme for enabling die reuse in 3D stacked products Electricity 3 Active
US7724567B2 Memory device and method of refreshing Physics 3 Active
US8958236B2 Memory cell flipping for mitigating SRAM BTI Physics 2 Active
US7133319B2 Programmable weak write test mode (PWWTM) bias generation having logic high output default mode Physics 2 Expired
US7076376B1 System and method for calibrating weak write test mode (WWTM) Physics 2 Expired
US12073919B2 Dual read port latch array bitcell Electricity 1 Active
US12033721B2 Split read port latch array bit cell Electricity 1 Active
US11233510B2 In memory logic functions using memory arrays Physics 1 Active
US10366734B2 Programmable write word line boost for low voltage memory operation Physics 1 Active
US11205477B2 Memory with expandable row width Physics 1 Active
US10783953B2 Memory with expandable row width Physics 1 Active
US11715514B2 Latch bit cells Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.