Semiconductor memory device having parallel test mode for simultaneously testing multiple memory cells
US6243309A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 19, 2000 |
| Grant date | Jun 5, 2001 |
| Priority date | — |
| Expiry date | Apr 19, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device having a parallel test mode for simultaneously testing a plurality of memory cells, comprising: a memory cell array having N numbers of memory cell blocks, wherein each memory cell block includes the plurality of memory cells and outputs first and second complementary data signals, the N being a positive integer; M numbers of first logical operation circuits responsive to a parallel test mode enable signal, each first logical operation circuit for carrying out a logical operation with respect to first and second complementary data signals outputted from at least two memory cell blocks, thereby generating first and second logical operation signals, wherein the N is greater than the M; a second logical operation circuit for carrying out the logical operation with respect to the first and second logical operation signals, thereby generating third and fourth logical operation signals; a pair of global data bus lines coupled between each of first logical operation circuit and said second logical operation circuit; and a buffer coupled to said second logical operation circuit for generating a test pass signal when the third and fourth logical operation signa…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.