Synchronous semiconductor memory device capable of selecting column at high speed
US6243320A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 11, 1999 |
| Grant date | Jun 5, 2001 |
| Priority date | — |
| Expiry date | Mar 11, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A command decoder receives an externally supplied command independently of an internal clock signal, decodes the command, generates a column access mode instruction signal, and activates a column address activation signal when the internal clock signal rises. An internal column address signal generating circuit generates an internal column address signal from an externally supplied address signal according to the column address activation signal. Accordingly, the internal column address is generated at an advanced timing to enable a following column selecting operation to be started at a faster timing. A synchronous semiconductor memory device capable of performing the column selecting operation at a high speed is thus provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.