Disposable-spacer damascene-gate process for SUB 0.05 .mu.m MOS devices
US6245619A · kind A · utility
28Cited by
1References
27Claims
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Key dates
| Filing date | Jan 21, 2000 |
| Grant date | Jun 12, 2001 |
| Priority date | — |
| Expiry date | Jan 21, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0217
Abstract
Techniques to fabricate sub-0.05 .mu.m MOSFET devices with Super-Halo doping profile which provide excellent short-channel characteristics are provided. The techniques utilize a damascene-gate process to obtain MOSFET structures with oxide thickness above the source/drain region independent of the gate-oxide thickness and a disposable-spacer technique for the formation of the Super-Halo doping profile.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.