Totally self-aligned transistor with tungsten gate
US6246096A · kind A · utility
1Cited by
6References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 24, 1998 |
| Grant date | Jun 12, 2001 |
| Priority date | — |
| Expiry date | Jun 24, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28079
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A totally self-aligned transistor with a tungsten gate. A single mask is used to align the source, drain, gate and isolation areas. Overlay error is greatly reduced by the use of a single mask for these regions. A mid-gap electrode is also self-aligned to the transistor. The electrode is preferably formed from tungsten metal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.