Efficient debug package design
US6246252A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 30, 1999 |
| Grant date | Jun 12, 2001 |
| Priority date | — |
| Expiry date | Jul 30, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method for providing for electrical testing of an integrated semiconductor substrate having at least two signal processing layers. The substrate may be provided with a protective layer of plastic, silicon, silicon oxide, silicon nitride or the like. A selected region of one substrate layer to be tested electrically is exposed by etching or otherwise forming a controllably small aperture any overlying substrate layer(s) away to expose at least one selected circuit trace in the selected region and applying a selected electrical signal to the trace. Optionally, a second aperture, spaced apart from the first aperture, can be formed to expose a second selected circuit trace so that propagation of a signal in one or more substrate circuits can be tested. The aperture cross-sectional shapes may be linear or curvilinear polygons or other suitable shapes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.