High-speed programmable logic architecture having active CMOS device drivers
US6246259A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 5, 1998 |
| Grant date | Jun 12, 2001 |
| Priority date | — |
| Expiry date | May 5, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/09429
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A field programmable logic device features an active device driver employing CMOS circuitry that includes a complementary CMOS inverter in electrical communication with a tri-state CMOS inverter, with the tri-state CMOS inverter defining a data input and a data output of the active device driver. The CMOS complementary inverter has an input node and an output node. The CMOS tri-state inverter is coupled to the input node, defining a control input for the active device driver.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.