Self-refresh test time reduction scheme
US6246619A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 7, 2000 |
| Grant date | Jun 12, 2001 |
| Priority date | — |
| Expiry date | Feb 7, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit for a DRAM is described which, when in test mode, notifies a tester when the self-refresh operation of a dynamic random access memory (DRAM) reaches various stages of completion. By signaling the tester when, i.e., 1/8, 1/4, 1/2, etc. of the self-refresh cycle is reached, the amount of time needed for verification of the self-refresh oscillator frequency is reduced correspondingly by a factor of 8, 4, 2 etc. The signaling of a partial test time is achieved by adding self-refresh status logic circuits which decode the high order most significant bits of the refresh address counter. The activation of the third most significant bit signals completion of 1/8th of the self-refresh cycle, the activation of the second most significant bit signals completion of 1/4th of the self-refresh cycle, the activation of the most significant bit signals completion of 1/2 of the self-refresh cycle, and deactivation of the most significant bit signals completion of the self-refresh cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.